1. Technical Field
The present invention relates in general to digital circuits and in particular to a digital multiplexer. Still more particularly, the present invention relates to an improved design of a static digital multiplexer.
2. Description of the Related Art
A multiplexer (MUX) is an electronic device, which is capable of accepting more than one input signal simultaneously and chooses one (or more) of the input signals as an output signal in response to the state of one or more select input. Conventional multiplexers are typically designed utilizing a combination of transistors from within the family of metal-oxide-semiconductor field-effect transistor (MOSFETs). Traditional static complementary MOS (CMOS) multiplexers have larger overall surface area and are typically relatively slow. Currently, the more common MUX designs being utilized include static pass gate and transmission gate multiplexers. Both of these MUXes have found extensive use in microprocessor designs due to their high density and relatively low power performance. They also provide higher speed than traditional static complementary MOS (CMOS) multiplexers.
A three input, static pass gate multiplexer (PG-MUX) is depicted in FIG. 1. PG-MUX 100 is usually built with N-type MOSFETs (NFETS) 101 because they have larger current driving capability than PFETs. Each input 109 of PG-MUX 100 is coupled to an inline inverter 111, whose output is coupled to the drain of NFET 101. A corresponding select signal 113 is connected to the gate of NFET 101. The source of each NFET 101 is coupled to a muxnode 108. Muxnode 108 is coupled to the drain of PFET 107 and to a second inverter 103 in turn coupled to output 115. NFET 101 in PG-MUX 100 is a passive device; therefore, second inverter 103 is interposed between muxnode 108 and output 115 to yield sufficient current driving capability for output 115.
In operation, the total delay of PG-MUX 100 is the sum of the delays of an input inverter 111, a pass transistor (NFET 101), and second inverter 103. As is well known in the art, PG-MUX 100 is effective for passing a high input signal (i.e., a xe2x80x9c1xe2x80x9d).
One major big drawback with a PG-MUX is that it cannot effectively and/or quickly pass a logic low input signal (i.e., a xe2x80x9c0xe2x80x9d). This is because the voltage at muxnode 108 is not the full power supply voltage, VDD, of PFET 107 but rather is reduced by the value of the threshold voltage (Vt) of PFET 107 (i.e., VDDxe2x88x92Vt). In order to pass a good logic xe2x80x9c1xe2x80x9d (i.e., inverted input xe2x80x9c0xe2x80x9d), a xe2x80x9chalf-latchxe2x80x9d 105 is utilized to pull-up PFET 107 to VDD. A typical half-latch 105 is implemented with PFET 107 whose gate is coupled in a feedback loop around second inverter 103. Utilization of half-latch 105 when passing a xe2x80x9c1xe2x80x9d followed by a xe2x80x9c0xe2x80x9d results in a significant switching penalty. By enabling a faster pass of a xe2x80x9c1xe2x80x9d with half-latch 105 a subsequent pass of a xe2x80x9c0xe2x80x9d is slowed down. This switching delay between xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d occurs because half-latch 105 continues to charge muxnode 108 until muxnode 108 is discharged to xe2x80x9c0xe2x80x9d and produces a xe2x80x9c1xe2x80x9d via inverter 103 to disable PFET 107. Therefore, a significant time is taken for the next input signal xe2x80x9c1xe2x80x9d to pass through as the half-latch 105 attempts to keep up the power at muxnode 108 after passing a logic xe2x80x9c1xe2x80x9d (i.e., inverted input signal 0), while the input is attempting to keep the power down. This xe2x80x9cfightxe2x80x9d causes additional current to be drawn, which leads to extra power dissipation and slower overall speeds.
A conventional three-input transmission gate multiplexer (TG-MUX) is illustrated in FIG. 2. Each input 209 of TG-MUX 200 is connected to inline inverter 211, whose output is coupled to the drain of NFET 201 and source of PFET 207. NFET 201 and PFET 207 are connected in parallel, source to drain. A corresponding select signal 213 is connected to the gate of NFET 201, while the complement of select signal 206 is connected to the gate of PFET 207. Complement of select signal 206 is generated by passing select signal 213 through second inverter 204. The outputs of the parallel branches of NFET 201 and PFET 207 are coupled together at muxnode 208. Muxnode 208 is connected to third inverter 203, which inverts the signal to produce output 115. Unlike a PG-MUX, TG-MUX 200 does not utilize a half-latch to pass a good xe2x80x9c0xe2x80x9d or good xe2x80x9c1xe2x80x9d. However, TG-MUX 200 is not necessarily faster than a PG-MUX, because TG-MUX uses additional parallel PFET 207, which is weaker than NFETs and adds extra delays due to a larger capacitance. In the design of TG-MUX 200, select signal 213 and its complement signal 206 have to be applied, and thus extra circuitry (i.e., second inverter 204) is required to generate complement signals 206. Utilizing extra circuitry 204 prevents select signal 213 and complement signal 206 from arriving at the same time due to the delays associated with second inverter 204. The xe2x80x9cunder-lappingxe2x80x9d of select signal 213 and complement signal 206 leads to longer xe2x80x9copenxe2x80x9d time of the gates of the transistors 201 and 207 respectively, which leads to cross DC currents through the input data paths. Such currents in turn result in speed degradation and extra power dissipation.
Improving the operation of the conventional designs of multiplexers has proven to be difficult. In particular, no major improvement in speed and low power applications has occurred recently.
The present invention recognizes that it would be desirable and beneficial to have a multiplexer circuit with improved speed performance over the traditional MUX circuits. It would further be desirable to provide a multiplexer circuit which operates with low power dissipation. A MUX design which incorporates both improved speed and power dissipation, while overcoming the afore-mentioned problems associated with traditional MUX designs would be a welcomed improvement. These and other benefits are provided by the invention described herein.
A high speed static multiplexer is disclosed comprising: (1) a plurality of data inputs and at least one select input; (2) an output; (3) a high voltage rail and a low voltage rail; (4) a pull-up circuit coupled between the output and the high voltage rail and further coupled to receive the data inputs and the select input so that the pull-up circuit generates a first logic state at the output in response to the selected data input having that first logic state; (5) and a pull-down circuit coupled between the output and the low voltage rail and further coupled to receive the data inputs and the select input, so that the pull-down circuit generates a second logic state at the output in response to the selected data input having that second logic state.
In a preferred embodiment, three N-type transistors are utilized in each of at least two sets of transistors corresponding to each data input. The data input is coupled to an inverter, which inverts the input data. The output of the inverter is coupled to the drain of the first transistor and to the gate of the third transistor. The pull-down circuit includes the second and third transistors, which are connected in series and enable a fast pull-down of the output during selection of a low input data. The select input circuit is coupled to the gate of the first transistor and the gate of the second transistor. The pull up circuit includes a P-type transistor, with its gate connected to the source of the first transistor. The output is coupled to the drain of the second transistor and is also operatively coupled to the drain of the P-type transistor. Operation of the P-type transistor allows selection of the output to occur with lower dissipation.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.